New Delhi: India launched an ambitious programme for developing next-generation semiconductor designs by the end of next year by using an open-source architecture known as RISC-V. Minister of State for Electronics and Information Technology Rajeev Chandrasekhar launched Digital India RISC-V (DIR-V) programme in New Delhi on Wednesday as the Ministry of Electronics and Information Technology (MeitY) will take premiere board membership of Switzerland based RISC-V International, a non-profit microprocessor architecture designer, to develop the country as a leader in RISC-V based technologies.
Chandrasekhar said DIR-V will catalyse India’s semiconductor startups making the country a semiconductor nation. The Digital India RISC-V programme will involve Indian startups, academic and research institutions and global tech giants that use RISC-V based semiconductors with the aim of developing India as a talent hub of the technology.
The programme aims at creating world-class microprocessors in the country, which can achieve industry-grade silicon & design wins by December next year. The government has set an aggressive milestone for commercial silicon of SHAKTI and VEGA processors and their design wins by December 2023 to make the country a supplier of RISC-V SoC (System on Chips) for servers, mobile devices, automotive, IoT and microcontrollers across the globe.
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Talking about his early days as an x-86 processor chip designer at Intel, Rajeev Chandrasekhar said many new processor architectures have gone through an initial period of development characterised by waves of innovations. “At some point, however, they all settled on a dominant design. ARM and x-86 are two such instruction set architectures- one of which is licensed and the other is sold, where industry consolidated in earlier decades,” said the minister.
He said RISC-V has emerged as a strong alternative to both ARM and x-86 in the last decade as it is an open-source system that does not require any licences, which enables its adoption by anyone in the semiconductor industry for various design purposes. In India, IIT Madras is one of the five development partners of the global RISC-V community, while the state-owned C-DAC has also developed a range of RISC-V processors and In Core semiconductors for releasing the Open-Source RISC-V Core Verification tool.
While IIT Madras developed a 32-bit microprocessor SHAKTI, the Centre for Development of Advanced Computing (CDAC) another 64-bit microprocessor named VEGA by using the RISC-V Open Source Architecture. Professor V Kamakoti, Director of IIT Madras, has been named as the chief architect and S Krishnakumar Rao has been named as programme manager for this programme.
